1. Field of the Invention
The present invention relates generally to automatic frequency control circuits (hereinafter referred to as AFC circuits), and more particularly, to an AFC circuit in which the frequency of a frequency-converted digital modulation signal to be supplied as an input to a demodulation circuit is stabilized.
2. Description of the Background Art
For demodulation of a digital modulation signal which is modulated by a digital signal, in general, an AFC circuit is employed in order to enhance demodulation characteristics of a demodulation circuit, particularly bit error rate characteristics. The AFC circuit serves to suppress various frequency fluctuations and stabilize a center frequency of a digital modulation signal to be supplied as an input to the demodulation circuit.
FIG. 1 is a block diagram showing one example of a conventional AFC circuit. With reference to FIG. 1, a frequency conversion circuit 1 includes an input band-pass filter (BPF) 101, a mixer 102, an IF band-pass filter 103 and an IF amplifier 104. Input band-pass filter 101 is supplied with a digital modulation signal received through an antenna. Input band-pass filter 101 serves to band-limit the applied digital modulation signal, to apply the band-limited signal to mixer 102. Mixer 102 mixes the digital modulation signal with a local oscillation signal applied from a voltage-controlled oscillator (VCO) 309, which will be described later, included in an AFC circuit 3, to supply an intermediate frequency signal as an output to IF band-pass filter 103. IF band-pass filter 103 band-limits the applied intermediate frequency signal, to supply the band-limited signal to IF amplifier 104. IF amplifier 104 amplifies the intermediate frequency signal, to apply the amplified signal to a demodulation circuit 2.
Demodulation circuit 2 includes a band-pass filter 201 for band-limitation, a phase detector 202 and a carrier reproduction circuit 203. Band-pass filter 201 limits the band of the intermediate frequency signal, which is a digital modulation signal, to improve a carrier-to-noise ratio (C/N) and enhance demodulation characteristics. The band-limited intermediate frequency signal is applied to phase detector 202 and then multiplied by carrier f.sub.L supplied as an input from carrier reproduction circuit 203, so that the digital modulation signal is demodulated. In the example shown in FIG. 1, the digital modulation signal is an example of a quadrature four phase modulation signal, in which two signals I and Q orthogonal to each other are demodulated as demodulation signals. Carrier reproduction circuit 203 synchronizes the carrier with the center frequency of the digital modulation signal in response to the demodulated two signals I and Q, to apply a synchronizing detection signal 306 serving as a determining signal for determining synchronization nonsynchronization to AFC circuit 3.
AFC circuit 3 includes a frequency divider 301, a reference oscillator 302, a phase comparator 303, a microprocessor 307, a D/A converter 308 and VCO 309. Frequency divider 301 serves to 1/A frequency-divider the digital modulation signal that has passed band-pass filter 201 in demodulation circuit 2. A frequency division output of frequency divider 301 is applied to phase comparator 303. Phase comparator 303 is supplied with a reference frequency signal by reference oscillator 302. Phase comparator 303 compares in phase the digital modulation signal, which is frequency-divided by frequency divider 301, and the reference frequency signal, to supply an error signal as an output. More specifically, phase comparator 303 supplies as an output an error signal 304 of plus (+) when the phase of the digital modulation signal is in advance of that of the reference frequency signal, and conversely the comparator supplies an error signal 305 of minus (-) when the phase of the digital modulation signal is delayed from that of the reference frequency signal. Error signals 304 and 305 applied from phase comparator 303 and synchronizing detection signal 306 applied from carrier reproduction circuit 203 of demodulation circuit 2 are applied to microprocessor 307. Microprocessor 307 applies data corresponding to error signals 304 and 305 and synchronizing detection signal 306 to D/A converter 308. D/A converter 308 converts the applied data into an analog signal, to supply an AFC voltage to VCO 309.
A description will now be given on an operation of the conventional AFC circuit shown in FIG. 1. First, if synchronizing detection signal 306 supplied as an output from carrier reproduction circuit 203 is at the level representing nonsynchronization, microprocessor 307 makes the data to be applied to D/A converter 308 variable. D/A converter 308 converts the variable data into an analog voltage, to supply the converted voltage to VCO 309. VCO 309 sweeps a frequency in response to the variable voltage, to supply the swept frequency to mixer 102. Mixer 102 sweeps a frequency in response to the signal from VCO 309, so that an output signal of frequency divider 301 varies. Phase comparator 301 compares in phase a digital modulation signal and a reference frequency signal. If carrier f.sub.L is synchronized with the digital modulation signal in the course that VCO 309 performs sweeping, carrier reproduction circuit 203 causes synchronizing detection signal 306 to attain the level representing synchronization. Accordingly, microprocessor 307 stops VCO 309 from sweeping and then controls VCO 309 so as to lower the oscillation frequency of VCO 309 in response to the (+) error signal of those two error signals 304 and 305 applied from phase comparator 303. Conversely, microprocessor 307 controls VCO 309 so as to make the oscillation frequency thereof higher in response to the (-) error signal.
As described above, microprocessor 307 controls VCO 309 via D/A converter 308 so that the frequency of the digital modulation signal to be applied to demodulation circuit 2 may be stable. In addition, in order to prevent the oscillation frequency of VCO 309 from being frequently altered when carrier f.sub.L is in synchronization with the digital modulation signal, an allowable error range is set in phase comparator 303, thereby suppressing the times that the oscillation frequency of VCO 309 is controlled, to suppress the frequency fluctuation of the reproduced carrier.
In the conventional AFC circuit shown in FIG. 1, since the digital modulation signal, which is applied as an input to phase comparator 303 and frequency-divided, has passed band-pass filter 201 for band limitation, the digital modulation signal is influenced by the characteristics of band-pass filter 201. Particularly, because of variations in phase characteristics and amplitude characteristics due to temperature variations, the digital modulation signal undergoes a phase modulation or amplitude modulation, so that the frequency of the frequency-divided digital modulation signal becomes higher or lower than the frequency which is inherently divider. This might cause an error in an error signal of phase comparator 303.
Further, a frequency division error occurs in an output of frequency divider 301 in the case of a low C/N ratio, thereby causing a frequency error. Since phase comparator 303 is employed as means for stabilizing a digital modulation signal, reference oscillator 302 becomes necessary, and also the structure of phase comparator 303 becomes complicated by the setting of the allowable error range. Moreover, in order to compress the expansion of a spectrum of the digital modulation signal, the digital modulation signal should finally be frequency-divided up to the frequency of approximately 10 kHz. If the frequency of the digital modulation signal is 100 MHz or more, the frequency must be divided by 10000 or more, resulting in the disadvantage that the number of stages of frequency divider 301 increases. In addition, there is another disadvantage that jitter is produced in the frequency-divided signal, thereby causing an adverse effect when a phase comparison is made by phase comparator 303.